This application claims the priority of Korean Patent Application No. 2003-22571, filed on Apr. 10, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reducing skew between column select lines (CSLs) and a CSL driving method.
2. Description of the Related Art
In dynamic random access memory (DRAM), an external address is decoded to generate a column address, and column select lines (CSLs) for memory cells are selected using the column address. Thus, it is important to reduce skew between the CSLs during selection of the CSLs so as to improve write and read operation speeds.
FIG. 1 is a block diagram illustrating a structure of a conventional semiconductor memory device with a CSL driving scheme. Referring to FIG. 1, a CSL enable master signal generator A11 receives an internal clock PCLKC and generates a CSL enable master signal EM, and a CSL disable master signal generator B11 receives the internal clock PCLKC and generates a CSL disable master signal DM. The internal clock PCLKC is generated from an external clock applied from outside the semiconductor memory device.
Next, a CSL enable controller E11 generates a CSL enable control signal EC in response to the CSL enable master signal EM and a CSL disable controller F11 generates a CSL disable control signal DC in response to the CSL disable master signal DM.
Next, a plurality of CSL drivers G11 through G14 drive CSLs CSL1 through CSL4 of a plurality of memory cell arrays H11 through M14, respectively, in response to a decoded column address (not shown), the CSL enable control signal EC, and the CSL disable control signal DC.
The conventional CSL driving scheme uses one CSL enable controller E11 and one CSL disable controller F11 so as to control all of the CSL drivers G11 through G14. As a result, a line for transmitting the signal EC output from the CSL enable controller and a line for transmitting the signal DC output from the CSL disable controller F11 are globally routed to all of the CSL drivers G11 through G14.
Accordingly, the loads on input terminals of the CSL drivers G11 through G14 depend on the positions of the memory cell arrays H11 through H14 and the CSL drivers G11 through G14. An increase in the load increases skew between the CSLs CSL1 through CSL4. This phenomenon places restrictions on improvement of write and read operation speeds of the semiconductor memory device.